1. Technical Field
The present disclosure relates to a wiring substrate and a method of manufacturing the same. More particularly, in the wiring substrate according to the present invention, conductor patterns are formed on a mounting surface of the wiring substrate on which an electronic component is to be mounted, and the whole surfaces of exposed surfaces consisting of contact surfaces, with which bumps of the electronic component is in contact, and both side surfaces of the conductor patterns are covered with a metal brazing layer, and each of the conductor patterns are electrically connected to a corresponding one of the bumps when the metal brazing layer is fused.
2. Related Art
As the wiring substrate having a mounting surface on which a semiconductor element as an electronic component is flip-chip mounted, JP-A-2005-268353 discloses a wiring substrate 10 shown in FIG. 8.
In the wiring substrate 10 shown in FIG. 8, conductor patterns 16, 16, . . . exposed from a solder resist 20 are formed on the mounting surface. As shown in FIG. 9, a solder layer is formed on exposed portions of the conductor patterns 16, 16, . . . respectively. This solder layer is formed by fusing solder powders as metal brazing powders that are adhered onto whole surfaces of the exposed surfaces of the conductor patterns 16, 16, . . . respectively. In JP-A-2005-268353, upon flip-chip mounting a semiconductor element 12 on the wiring substrate 10, as shown in FIG. 9, the solder layers formed on exposed surfaces of the conductor patterns 16, 16, . . . , are fused, and then top ends of bumps 22 of the semiconductor element 12 are brought into contact with corresponding widened portions 16a, 16a, . . . , of the conductor patterns 16, 16, . . . , being covered with a fused solder 100 respectively. At this time, the fused solder 100 that covers the whole surface of the exposed surface of the conductor pattern 16 is gathered around the bump 22 of the semiconductor element 12 by a surface tension, and the bump 22 and the conductor pattern 16 are bonded together and electrically connected each other.
According to the wiring substrate disclosed in JP-A-2005-268353 (the wiring substrate 10 shown in FIG. 8), the fused solder 100 that covers the whole surface of the exposed surface of the conductor pattern 16 can be used in bonding the bump 22 of the semiconductor element 12 and the conductor pattern 16. Hence, without fail, the bump 22 and the conductor pattern 16 can be electrically connected each other.
However, in the wiring substrate 10 shown in FIG. 8 and FIG. 9, the conductor patterns 16, 16, . . . , covered with the solder are formed on a flat mounting surface. Therefore, in such a situation that the conductor patterns 16, 16, . . . , should be formed at a narrow pitch on the wiring substrate 10 to attain a higher density of the conductor patterns 16, 16, . . . , in some cases, a bridge of the fused solder 100 is produced between the adjacent conductor patterns 16, 16, . . . , or a solder residue is caused, as shown in FIG. 10. Even though the bridge of the fused solder 100 or the solder residue is caused, no industrial removing means for removing them are not present. As a result, the wiring substrate 10 in which the bridge of the fused solder 100 or the solder residue is caused must be inevitably regarded as a defective product.